The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.
Metrics
Affected Vendors & Products
References
History
Wed, 26 Nov 2025 11:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Amd
Amd alveo Amd versal Arm Arm cortex-a Arm trusted Firmware-a |
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| Vendors & Products |
Amd
Amd alveo Amd versal Arm Arm cortex-a Arm trusted Firmware-a |
Mon, 24 Nov 2025 18:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Metrics |
ssvc
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Sun, 23 Nov 2025 17:30:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state. | |
| Weaknesses | CWE-1284 | |
| References |
| |
| Metrics |
cvssV4_0
|
Status: PUBLISHED
Assigner: AMD
Published: 2025-11-23T17:15:28.948Z
Updated: 2025-11-24T17:18:45.934Z
Reserved: 2025-07-23T15:01:52.882Z
Link: CVE-2025-54515
Updated: 2025-11-24T17:18:42.716Z
Status : Awaiting Analysis
Published: 2025-11-23T18:15:55.163
Modified: 2025-11-25T22:16:42.557
Link: CVE-2025-54515
No data.